\doxysection{RCC\+\_\+\+PLL2\+Init\+Type\+Def Struct Reference}
\hypertarget{struct_r_c_c___p_l_l2_init_type_def}{}\label{struct_r_c_c___p_l_l2_init_type_def}\index{RCC\_PLL2InitTypeDef@{RCC\_PLL2InitTypeDef}}


PLL2 Clock structure definition.  




{\ttfamily \#include $<$stm32h7xx\+\_\+hal\+\_\+rcc\+\_\+ex.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___p_l_l2_init_type_def_a3ad5fd858d8ed0ac9f755f7c695ffb31}{PLL2M}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___p_l_l2_init_type_def_a671c143593021bcbee5b2817e67bc297}{PLL2N}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___p_l_l2_init_type_def_ad008f3ff2c131bbe35eae73a3942aa16}{PLL2P}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___p_l_l2_init_type_def_ad94606003e7cf43fcc864776ee61341d}{PLL2Q}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___p_l_l2_init_type_def_a3871c154ba3986c590adeca367edd766}{PLL2R}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___p_l_l2_init_type_def_a64be6eb14e50c40fa0e8133de46d1972}{PLL2\+RGE}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___p_l_l2_init_type_def_ac30edcebfff52e53c3619688c5a0680d}{PLL2\+VCOSEL}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___p_l_l2_init_type_def_a7e47d1e68b48413a84a0991ed684b5cd}{PLL2\+FRACN}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
PLL2 Clock structure definition. 

\label{doc-variable-members}
\Hypertarget{struct_r_c_c___p_l_l2_init_type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_r_c_c___p_l_l2_init_type_def_a7e47d1e68b48413a84a0991ed684b5cd}\index{RCC\_PLL2InitTypeDef@{RCC\_PLL2InitTypeDef}!PLL2FRACN@{PLL2FRACN}}
\index{PLL2FRACN@{PLL2FRACN}!RCC\_PLL2InitTypeDef@{RCC\_PLL2InitTypeDef}}
\doxysubsubsection{\texorpdfstring{PLL2FRACN}{PLL2FRACN}}
{\footnotesize\ttfamily \label{struct_r_c_c___p_l_l2_init_type_def_a7e47d1e68b48413a84a0991ed684b5cd} 
uint32\+\_\+t RCC\+\_\+\+PLL2\+Init\+Type\+Def\+::\+PLL2\+FRACN}

PLL2\+FRACN\+: Specifies Fractional Part Of The Multiplication Factor for PLL2 VCO It should be a value between 0 and 8191 \Hypertarget{struct_r_c_c___p_l_l2_init_type_def_a3ad5fd858d8ed0ac9f755f7c695ffb31}\index{RCC\_PLL2InitTypeDef@{RCC\_PLL2InitTypeDef}!PLL2M@{PLL2M}}
\index{PLL2M@{PLL2M}!RCC\_PLL2InitTypeDef@{RCC\_PLL2InitTypeDef}}
\doxysubsubsection{\texorpdfstring{PLL2M}{PLL2M}}
{\footnotesize\ttfamily \label{struct_r_c_c___p_l_l2_init_type_def_a3ad5fd858d8ed0ac9f755f7c695ffb31} 
uint32\+\_\+t RCC\+\_\+\+PLL2\+Init\+Type\+Def\+::\+PLL2M}

PLL2M\+: Division factor for PLL2 VCO input clock. This parameter must be a number between Min\+\_\+\+Data = 1 and Max\+\_\+\+Data = 63 \Hypertarget{struct_r_c_c___p_l_l2_init_type_def_a671c143593021bcbee5b2817e67bc297}\index{RCC\_PLL2InitTypeDef@{RCC\_PLL2InitTypeDef}!PLL2N@{PLL2N}}
\index{PLL2N@{PLL2N}!RCC\_PLL2InitTypeDef@{RCC\_PLL2InitTypeDef}}
\doxysubsubsection{\texorpdfstring{PLL2N}{PLL2N}}
{\footnotesize\ttfamily \label{struct_r_c_c___p_l_l2_init_type_def_a671c143593021bcbee5b2817e67bc297} 
uint32\+\_\+t RCC\+\_\+\+PLL2\+Init\+Type\+Def\+::\+PLL2N}

PLL2N\+: Multiplication factor for PLL2 VCO output clock. This parameter must be a number between Min\+\_\+\+Data = 4 and Max\+\_\+\+Data = 512 or between Min\+\_\+\+Data = 8 and Max\+\_\+\+Data = 420(\texorpdfstring{$\ast$}{*}) (\texorpdfstring{$\ast$}{*}) \+: For stm32h7a3xx and stm32h7b3xx family lines. \Hypertarget{struct_r_c_c___p_l_l2_init_type_def_ad008f3ff2c131bbe35eae73a3942aa16}\index{RCC\_PLL2InitTypeDef@{RCC\_PLL2InitTypeDef}!PLL2P@{PLL2P}}
\index{PLL2P@{PLL2P}!RCC\_PLL2InitTypeDef@{RCC\_PLL2InitTypeDef}}
\doxysubsubsection{\texorpdfstring{PLL2P}{PLL2P}}
{\footnotesize\ttfamily \label{struct_r_c_c___p_l_l2_init_type_def_ad008f3ff2c131bbe35eae73a3942aa16} 
uint32\+\_\+t RCC\+\_\+\+PLL2\+Init\+Type\+Def\+::\+PLL2P}

PLL2P\+: Division factor for system clock. This parameter must be a number between Min\+\_\+\+Data = 2 and Max\+\_\+\+Data = 128 odd division factors are not allowed \Hypertarget{struct_r_c_c___p_l_l2_init_type_def_ad94606003e7cf43fcc864776ee61341d}\index{RCC\_PLL2InitTypeDef@{RCC\_PLL2InitTypeDef}!PLL2Q@{PLL2Q}}
\index{PLL2Q@{PLL2Q}!RCC\_PLL2InitTypeDef@{RCC\_PLL2InitTypeDef}}
\doxysubsubsection{\texorpdfstring{PLL2Q}{PLL2Q}}
{\footnotesize\ttfamily \label{struct_r_c_c___p_l_l2_init_type_def_ad94606003e7cf43fcc864776ee61341d} 
uint32\+\_\+t RCC\+\_\+\+PLL2\+Init\+Type\+Def\+::\+PLL2Q}

PLL2Q\+: Division factor for peripheral clocks. This parameter must be a number between Min\+\_\+\+Data = 1 and Max\+\_\+\+Data = 128 \Hypertarget{struct_r_c_c___p_l_l2_init_type_def_a3871c154ba3986c590adeca367edd766}\index{RCC\_PLL2InitTypeDef@{RCC\_PLL2InitTypeDef}!PLL2R@{PLL2R}}
\index{PLL2R@{PLL2R}!RCC\_PLL2InitTypeDef@{RCC\_PLL2InitTypeDef}}
\doxysubsubsection{\texorpdfstring{PLL2R}{PLL2R}}
{\footnotesize\ttfamily \label{struct_r_c_c___p_l_l2_init_type_def_a3871c154ba3986c590adeca367edd766} 
uint32\+\_\+t RCC\+\_\+\+PLL2\+Init\+Type\+Def\+::\+PLL2R}

PLL2R\+: Division factor for peripheral clocks. This parameter must be a number between Min\+\_\+\+Data = 1 and Max\+\_\+\+Data = 128 \Hypertarget{struct_r_c_c___p_l_l2_init_type_def_a64be6eb14e50c40fa0e8133de46d1972}\index{RCC\_PLL2InitTypeDef@{RCC\_PLL2InitTypeDef}!PLL2RGE@{PLL2RGE}}
\index{PLL2RGE@{PLL2RGE}!RCC\_PLL2InitTypeDef@{RCC\_PLL2InitTypeDef}}
\doxysubsubsection{\texorpdfstring{PLL2RGE}{PLL2RGE}}
{\footnotesize\ttfamily \label{struct_r_c_c___p_l_l2_init_type_def_a64be6eb14e50c40fa0e8133de46d1972} 
uint32\+\_\+t RCC\+\_\+\+PLL2\+Init\+Type\+Def\+::\+PLL2\+RGE}

PLL2\+RGE\+: PLL2 clock Input range This parameter must be a value of \doxylink{group___r_c_c___p_l_l2___v_c_i___range}{RCC PLL2 VCI Range} \Hypertarget{struct_r_c_c___p_l_l2_init_type_def_ac30edcebfff52e53c3619688c5a0680d}\index{RCC\_PLL2InitTypeDef@{RCC\_PLL2InitTypeDef}!PLL2VCOSEL@{PLL2VCOSEL}}
\index{PLL2VCOSEL@{PLL2VCOSEL}!RCC\_PLL2InitTypeDef@{RCC\_PLL2InitTypeDef}}
\doxysubsubsection{\texorpdfstring{PLL2VCOSEL}{PLL2VCOSEL}}
{\footnotesize\ttfamily \label{struct_r_c_c___p_l_l2_init_type_def_ac30edcebfff52e53c3619688c5a0680d} 
uint32\+\_\+t RCC\+\_\+\+PLL2\+Init\+Type\+Def\+::\+PLL2\+VCOSEL}

PLL2\+VCOSEL\+: PLL2 clock Output range This parameter must be a value of \doxylink{group___r_c_c___p_l_l2___v_c_o___range}{RCC PLL2 VCO Range} 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+STM32\+H7xx\+\_\+\+HAL\+\_\+\+Driver/\+Inc/\mbox{\hyperlink{stm32h7xx__hal__rcc__ex_8h}{stm32h7xx\+\_\+hal\+\_\+rcc\+\_\+ex.\+h}}\end{DoxyCompactItemize}
